Various encoders, decoders, and other circuits use finite state machines (“FSMs”). Generally, an FSM makes a state transition sequentially for each data item input. For example, for a 64B/66B encoder/decoder in an Ethernet Physical Coding Sublayer (“PCS”), a state transition is made for every 64-bit data block. For high throughput, wide data buses, such as for example 1280 bits (i.e., 20 64-bit data blocks), are used to process a large amount of data per clock cycle at high clock rate. In the past, this involved cascading multiple copies of the same FSM circuit so as to process multiple data blocks per clock cycle. However, the length of the critical path for state propagation is generally linearly increased, which offsets negatively the throughput increase in such cascaded FSM circuits. Accordingly, it has been problematic to meet a timing requirement in a 400 Gb/s PCS with a clock rate above 300 MHz.
Hence, it is desirable and useful to provide an FSM circuit that facilitates high data rates for meeting or exceeding high throughput of high-speed applications.